"Mastering Digital Synthesis: A Synopsys Design Compiler (DC) Tutorial."
DC is heavily reliant on Tcl scripting. Here are some essential commands you will use frequently:
For this tutorial, we use for reproducibility.
The fundamental goal of Design Compiler is to transform high-level hardware descriptions (Verilog, SystemVerilog, or VHDL) into a technology-specific gate-level representation. This process is governed by four primary stages: ASIC Design Flow Tutorial Using Synopsys Tools synopsys design compiler tutorial 2021
current_design $DESIGN_NAME link
The Design Compiler execution flow consists of five distinct stages: ingestion, elaboration, constraint definition, optimization, and export.
report_timing > ./reports/timing.rpt
Design Compiler offers structural transformation flags to fix critical timing violations:
However, a tutorial is only the first step. The real skill lies in reading the *.rpt files and deciphering why the compiler made specific choices. Your next steps should be:
# .synopsys_dc.setup # Define search paths for source files and libraries set search_path [list . ../rtl ../libs] # Target library specified by the foundry (used for gate mapping) set target_library [list typical.db] # Link library includes target library and synthetic libraries (DesignWare) set link_library [list * typical.db dw_foundation.sldb] # Symbolic library for graphical representation set symbol_library [list typical.sdb] # Define command log and history files set view_command_log_file "./command.log" define_design_lib WORK -path ./WORK Use code with caution. 3. Design Compiler Execution Modes This process is governed by four primary stages:
Before launching the tool, you must configure your environment and setup files.
# Assume external logic takes 2.5ns to drive the input port 'data_in' set_input_delay 2.5 -clock sys_clk [get_ports data_in] # Assume external logic requires 3.0ns of setup time before the next clock edge set_output_delay 3.0 -clock sys_clk [get_ports data_out] Use code with caution. Environment and Area Attributes
write_sdc ./results/top.sdc
sh mkdir -p $work_dir $report_dir $db_dir
Finally, you save the synthesized database as a .ddc file (Synopsys's binary format), the gate-level netlist as a .v file, and the final constraints as a .sdc file for use in other tools like PrimeTime for STA or IC Compiler II for physical design.